1. Field of the Invention
The present invention relates to a bipolar transistor having a polysilicon emitter and, in particular, to a bipolar device formed utilizing a single polysilicon layer and a tilted ion-implanted link base region that may readily be incorporated into existing CMOS processes.
2. Description of the Related Art
The majority of integrated circuit designs employ some form of digital signal processing. These conventional logic structures dictate the use of complementary MOS (CMOS) device architectures. In the pursuit of enhanced performance and greater flexibility, IC designers have increasingly relied upon circuits that combine both bipolar and MOS transistor technologies. For maximum process efficiency, a polysilicon bipolar transistor should be formed in a process flow that shares as many processing steps as possible with a standard CMOS process flow. However, creating a process flow that successfully integrates bipolar and MOS architectures can pose a significant challenge.
FIG. 1A shows a cross-sectional view of a conventional NPN bipolar transistor device which includes a diffused polysilicon emitter structure formed from a single polysilicon layer. Conventional single-poly NPN bipolar transistor 100 lies within N-well 102 formed in P-type silicon 104. Conventional single-poly bipolar transistor 100 is electrically isolated from the effects of adjacent semiconductor devices by inter-device isolation structures 106.
NPN transistor 100 further includes a buried N+ collector layer 108 connected to collector contact 110 by N+ sinker structure 112. Collector contact 110 may be conveniently formed during the source/drain implant steps of an associated CMOS process. Collector contact 110 and sinker 112 are electrically insulated from the remainder of transistor 100 by intra-device isolation structure 114.
Bipolar transistor 100 also includes P-type base 116 having a P+ base contact 118. Base 116 consists of intrinsic base region 116a and extrinsic base region 116b. As used in this patent application, the term xe2x80x9cintrinsic basexe2x80x9d refers to that portion of the base directly underneath the collector. The term xe2x80x9cextrinsic basexe2x80x9d refers to that portion of the base region of the bipolar transistor which is not directly underneath the collector.
Base 116 may be formed within N-well 102 during implantation of dopant to form the lightly doped drain (pldd) regions of associated CMOS devices. Base contact 118 may be formed during the source/drain implant of associated CMOS devices.
Bipolar transistor 100 further includes diffused polysilicon emitter structure 122. Emitter 122 includes a polysilicon contact component 122a and a diffused single crystal component 122b. Polysilicon contact component 122a may be formed from the same N-type polysilicon layer used to create the gates of associated CMOS devices. Diffused single crystal component 122b is formed by thermal diffusion of N-type dopant from polysilicon contact component 122a into base 116.
Conventional single-poly bipolar transistor 100 also includes an overlying dielectric material 124.
While the conventional single-poly bipolar transistor shown in FIG. 1A is useful in many applications, it suffers from the disadvantage of exhibiting a relatively high base resistance.
FIG. 1B shows an enlarged cross-sectional view of an edge portion of the emitter base junction of the device of FIG. 1A. During operation of bipolar transistor 100, the bulk of the charge traveling between base contact 118 and intrinsic base 116a must traverse conductive path 126.
Because the overlying interconnect must make contact with both polysilicon emitter component 122a and base contact region 118, regions 116a and 118 must be separated to ensure electrical isolation between the contacts. Therefore, conductive path 126 traverses a relatively long distance. The length of path 126 in turn creates high electrical resistance.
The elevated high base resistance acts to degrade device performance. In particular, equation (I) determines the maximum frequency of switching of the transistor:                               (          I          )                ⁢                  xe2x80x83                ⁢                  f          MAX                    =                        f          T                /                  (                      8            ⁢            π            ⁢                          xe2x80x83                        ⁢                          C              JBC                        ⁢                          R              B                                )                      ,          where      ⁢              :                                                      f            MAX                    =                      frequency            ⁢                          xe2x80x83                        ⁢            at            ⁢                          xe2x80x83                        ⁢            which            ⁢                          xe2x80x83                        ⁢            unilateral            ⁢                          xe2x80x83                        ⁢            power            ⁢                          xe2x80x83                        ⁢            gain            ⁢                          xe2x80x83                        ⁢            is            ⁢                          xe2x80x83                        ⁢            unity                                                                    f            T                    =                      unity            ⁢                          xe2x80x83                        ⁢            gain            ⁢                          xe2x80x83                        ⁢            cutoff            ⁢                          xe2x80x83                        ⁢            frequency                                                                    C            JBC                    =                      base            ⁢                          -                        ⁢            collector            ⁢                          xe2x80x83                        ⁢            junction            ⁢                          xe2x80x83                        ⁢            capacitance                                                                    R            B                    =                      base            ⁢                          xe2x80x83                        ⁢            resistance            ⁢                          xe2x80x83                        ⁢                          (                              intrinsic                +                extrinsic                            )                                          
Thus, a higher overall base resistance will reduce the switching frequency of the transistor. A low fMAX is particularly problematic given the extremely rapid switching frequencies demanded by modern, high-speed digital applications.
In order to reduce base resistance and thereby overcome this disadvantage, device engineers have implemented a double-polysilicon bipolar transistor design. FIG. 2A shows a cross-sectional view of a conventional double-poly NPN bipolar transistor device.
Double-poly NPN bipolar transistor 200 lies within N-well 202 formed within P-type silicon 204. Conventional double-poly bipolar transistor 200 is electrically isolated from the effects of adjacent semiconductor devices by inter-device isolation structures 206.
Bipolar transistor 200 includes a buried N+ collector layer 208 connected to collector contact 210 by N+ sinker structure 212. Collector contact 210 may conveniently be formed during the source/drain implant steps of an associated CMOS process. Collector contact 210 and sinker 212 are electrically isolated from remainder of transistor 200 by intra-device isolation structure 214.
Bipolar transistor 200 further includes a doped base layer 216, which includes an intrinsic base region 216a. Diffused polysilicon base 218 overlies and is separated from doped base layer 216 by a first dielectric layer 219. Diffused polysilicon base 218 includes a polysilicon contact component 218a and a diffused single crystal silicon component 218b. 
Polysilicon base contact 218a is formed from a P-type polysilicon layer. Single crystal base component 218b is formed by diffusion of P type dopant from polysilicon base contact 218a into doped base layer 216.
Bipolar transistor 200 further features diffused polysilicon emitter structure 222 which is formed over and separated from polysilicon base 218a by second dielectric layer 224. Diffused polysilicon emitter structure 222 includes polysilicon emitter contact component 222a and single crystal diffused emitter component 222b. 
Polysilicon emitter contact 222a is formed from a second doped polysilicon layer of N-type conductivity, as could be used to form the gates of associated CMOS transistors Single crystal emitter component 222b is formed by diffusion of N-type dopant from polysilicon component 222a into doped base layer 216.
FIG. 2B is an enlarged view of an edge portion of the emitter/base junction of the device of FIG. 2A. FIG. 2B reveals that because single crystal base component 218b is self-aligned to single crystal emitter component 222b, regions 218b and 222b are separated by only the width of second dielectric layer 224 (typically less than 0.4 xcexcm). This configuration is made possible by the presence of polysilicon base contact component 218a, and single crystal base component 218b, which provide highly doped, low-resistance conductive path 226 to intrinsic base 216a. 
While the conventional double-poly bipolar transistor structure addresses significant performance disadvantages of the conventional single-poly bipolar transistor, this design suffers from a serious disadvantage in the form of more complex processing. Specifically, the double-poly bipolar transistor depicted in FIG. 2A requires additional polysilicon deposition, implant, masking, and etching steps to create the diffused polysilicon base structure. Each of these added steps confers a process penalty in the form of reduced yield and increased cost.
In particular, utilizing separate polysilicon layers can introduce a xe2x80x9cpoly stringerxe2x80x9d problem. This xe2x80x9cpoly stringerxe2x80x9d problem is a result of deposition of a second polysilicon layer occurring over sharp corners of raised features of a first polysilicon layer. Such a double-polysilicon structure is difficult to etch without leaving behind filaments (xe2x80x9cstringersxe2x80x9d) from the second polysilicon layer.
This xe2x80x9cpoly stringerxe2x80x9d problem can be eliminated by forming an intervening dielectric layer between the two polysilicon layers. However, this solution requires additional processing steps to form the dielectric layer. These additional steps further degrade overall throughput and thus increase expense.
The enhanced complexity in fabricating a double-poly bipolar transistor is particularly troublesome when the processing requirements of associated CMOS devices are taken into account.
Therefore, there is a need in the art for a bipolar transistor structure compatible with a CMOS process flow that maintains low base resistance while preserving process simplicity.
The present invention proposes a bipolar transistor compatible with CMOS processes that utilizes only a single layer of polysilicon. The design in accordance with the present invention maintains lowered base resistance and superior performance associated with conventional double-poly bipolar transistors, while preserving process simplicity.
The present invention utilizes implantation of dopant to form the intrinsic base through the same nitride window in which a diffused polysilicon emitter structure will later be created. Following polysilicon deposition, implant, and etching, a tilted implant is used to form a link base region.
This link base creates a short, highly doped, low resistance path between the base contact and the diffused polysilicon emitter.
Because the present invention employs only a single polysilicon layer, the process flow is much simpler than that associated with formation of the conventional double-poly structure. This advantage is even more apparent where tilted ion implantation must already be employed in the process to form an LDMOS or some other associated semiconductor structure.
A first embodiment of a process for forming a bipolar transistor in accordance with the present invention comprises the steps of forming a well of a first conductivity type in a semiconductor material, forming a buried highly doped collector region of the first conductivity type in the well, and forming a dielectric layer having a window over the collector region in the well. Next, dopant of a second conductivity type opposite the first conductivity type is introduced through the window to form an intrinsic base region. A polysilicon layer is then formed over the dielectric layer and within the window. Dopant of the first conductivity type is then introduced into the polysilicon layer, and the polysilicon layer is etched to form a polysilicon emitter contact component structure extending at least over the window. Dopant of the first conductivity type is then introduced into the semiconductor material directly underneath the polysilicon emitter contact component and above the intrinsic base to form a single crystal emitter component, and dopant of the second conductivity type is ion implanted at an angle of less than 90xc2x0 to the semiconductor material to form a link base region, the link base region extending underneath the polysilicon emitter contact component and overlapping the intrinsic base region.
A first embodiment of a single-poly bipolar transistor in accordance with the present invention comprises a well of a first conductivity type formed in a semiconductor material, a subsurface collector region of the first conductivity type located in the well, and an intrinsic base region of the second conductivity type formed in the well above the collector region. A single crystal emitter component of the first conductivity type is formed in the well above the intrinsic base region. A polysilicon emitter contact component of the first conductivity type is formed over the intrinsic emitter. A base contact region is formed in the well adjacent to the polysilicon emitter component, and a link base region of the second conductivity type is formed in the well by tilted ion implantation, the link base extending laterally underneath the polysilicon emitter contact component and overlapping with the intrinsic base region and the base contact region.
The features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings.